1. Field of the Invention
The present invention relates generally to the field of parallel graphics processing and, more specifically, to sharing a data crossbar for reads and writes in the data cache.
2. Description of the Related Art
A computing architecture may be designed such that multiple parallel threads within a thread group can all access memory locations within an L1 cache. An L1 cache memory is often laid out as a series of banks including memory locations that can be uniquely identified. Each thread in the thread group can read data from or write data to any memory location within a bank of the L1 cache memory.
To transmit data to/from the L1 cache memory, an L1 cache often implements data crossbars. The data crossbars are configured to transmit data retrieved from the L1 cache memory to clients (reads) and from the clients to the L1 cache memory (writes). In a typical architecture, a data crossbar is dedicated for transmitting read data and another data crossbar is dedicated for transmitting write data. In such an architecture, a significant amount of on-chip die space is consumed for data crossbars. Such a design is both architecturally undesirable and expensive to produce.
Accordingly, what is needed in the art is an L1 cache crossbar design that transmits data to/from the L1 cache memory more efficiently.